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CMF20120D-Silicon Carbide Power MOSFET
1200V 80 m
Z-FETTM MOSFET
N-Channel Enhancement Mode
Rev. CMF20120D
Subject to change without notice. www.cree.com/power
1
CMF20120D-Silicon Carbide Power MOSFET
Z-FETTM MOSFET
Features
VDS RDS(on) = 1200 V = 80 m
N-Channel Enhancement Mode
Package
ID(MAX)@TC=25C = 33 A
* * * * * *
Industry Leading RDS(on) High Speed Switching Low Capacitances Easy to Parallel Simple to Drive Pb-Free Lead Plating, ROHS Compliant, Halogen Free
D D
G G
TO-247-3
S S
Benefits
* * * *
HigherSystemEfficiency Reduced Cooling Requirements Avalanche Ruggedness Increased System Switching Frequency
Part Number
CMF20120D
Package
TO-247-3
Applications
Maximum Ratings
Symbol
* * *
Solar Inverters High Voltage DC/DC Converters Motor Drives
Parameter
Continuous Drain Current
Value
33 17 78 2.2 1.5 20 -5/+25 150 -55 to +125 260 1 8.8
Unit
A
Test Conditions
VGS@20V, TC =25C VGS@20V, TC =100C
Note
ID IDpulse EAS EAR IAR VGS Ptot TJ , Tstg TL Md
Pulsed Drain Current Single Pulse Avalanche Energy Repetitive Avalanche Energy Repetitive Avalanche Current Gate Source Voltage Power Dissipation Operating Junction and Storage Temperature Solder Temperature Mounting Torque
A J J A V W C C
Pulse width tP limited by Tjmax TC =25C ID = 20A, VDD = 50 V, L = 9.5 mH tAR limited by Tjmax ID = 20A, VDD = 50 V, L = 3 mH tAR limited by Tjmax
TC=25C
1.6mm (0.063") from case for 10s
Nm M3 or 6-32 screw lbf-in
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CMF20120D Rev. -
Table of Contents
Features.................................................................................................................2 Benefits...........................................................................................................2 Applications.....................................................................................................2 Maximum Ratings...................................................................................................2 Table of Contents....................................................................................................3 Applications Information........................................................................................4 ESD Ratings............................................................................................................7 Electrical Characteristics........................................................................................8 Reverse Diode Characteristics.................................................................................8 Thermal Characteristics..........................................................................................8 Gate Charge Characteristics....................................................................................8 Typical Performance..............................................................................................................9 Clamped Inductive Switch Testing Fixture..............................................................11 Package Dimensions.............................................................................................12 Recommended Solder Pad Layout..........................................................................13 Notice..............................................................................................................14
3
CMF20120D Rev. -
Applications Information The Cree SiC MOSFET has removed the upper voltage limit of silicon MOSFETs. However, there are some differences in characteristics when compared to what is usually expected with high voltage silicon MOSFETs. These differences need to be carefullyaddressedtogetmaximumbenefitfromtheSiCMOSFET.Ingeneral, although the SiC MOSFET is a superior switch compared to its silicon counterparts, it should not be considered as a direct drop-in replacement in existing applications. There are two key characteristics that need to be kept in mind when applying the SiC MOSFETs: modest transconductance requires that VGS needs to be 20 V to optimize performance. This can be see in the Output and Transfer Characteristics shown in Figures 1-3. The modest transconductance also affects the transition where the device behaves as a voltage controlled resistance to where it behaves as a voltage controlled current source as a funtion of VDS. The result is that the transition occurs over higher values of VDS than are usually experienced with Si MOSFETs and IGBTs. This might affect the operation anti-desaturation circuits, especially if the circuit takes advantage of the device entering the constant current region at low values of forward voltage. The modest transconductance needs to be carefully considered in the design of the gatedrivecircuit.Thefirstobviousrequirementisthatthegatebecapable of a >22 V (+20 V to -2V) swing. The recommended on state VGS is +20 V and the recommended off state VGS is between -2 V to -5 V. Please carefully note that although the gate voltage swing is higher than the typical silicon MOSFETs and IGBTs, the total gate charge of the SiC MOSFET is considerably lower. In fact, the product of gate voltage swing and gate charge for the SiC MOSFET is lower than comparable silicon devices. The gate voltage must have a fast dV/dt to achieve fast switching times which indicates that a very low impedance driver is necessary. Lastly,thefidelityofthegatedrivepulsemustbecarefullycontrolled.Thenominal 2.5V threshold voltage is 2.5V and the device is not fully on (dVDS/dt0) until the VGS is above 16V. This is a noticeably wider range than what is typically experienced with silicon MOSFETs and IGBTs. The net result of this is that the SiC MOSFET has a somewhat lower `noise margin'. Any excessive ringing that is present on the gate drive signal could cause unintentional turn-on or partial turn-off of the device. The gate resistance should be carefully selected to ensure that the gate drive pulse is adequatelydampened.Tofirstorder,thegatecircuitcanbeapproximatedasa simple series RLC circuit driven by a voltage pulse as shown below.
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CMF20120D Rev. -
RLOOP
LLOOP
=

RLOOP CGATE 1 2 LLOOP
VPULSE
CGATE
RLOOP 2
LLOOP CGATE
As shown, minimizing LLOOP needed for critical minimizes the value of RLOOP dampening. Minimizing LLOOP also minimizes the rise/fall time. Therefore, it is strongly recommended that the gate drive be located as close to the SiC MOSFET MOSFET is 5. as possible to minimize LLOOP. The internal gate resistance of the SiC Anexternalresistanceof6.8wasusedtocharacterizethisdevice. Lowervaluesofexternalgateresistancecanbeusedsolongasthegatefidelityis maintained. In the event that no external gate resistance is used, it is suggested that the gate current be checked to indirectly verify that there is no ringing present in the gate circuit. This can be accomplished with a very small current transformer. A recommended setup is a two-stage current transformer as shown below:
IG SENSE
VCC GATE DRIVER
GATE DRIVE INPUT
+ VEE
T1
SiC DMOSFET

5
CMF20120D Rev. -
Stray inductance on source lead causes load di/dt to be fed back into gate drive which causes the following: * Switchdi/dtislimited * Couldcauseoscillation
LOAD CURRENT
Kelvingateconnectionwithseparate sourcereturnishighlyrecommended
20V 20V R GATE
DRIVE
R GATE
SiC DMOS
DRIVE
SiC DMOS
L STRAY
LOAD CURRENT
L STRAY
A schematic of the gate driver circuit used for characterization of the SiC MOSFET is shown below:
+VCC +VCC
THESE COMPONENTS ARE LOCATED ON THE -VEE PLANE
C1 10u -VEE C2 100n -VEE C4 100n -VEE C5 100n -VEE C8
THESE COMPONENTS ARE LOCATED ON THE GND PLANE
C3 10u GND +VCC C6 10u -VEE -VEE 1 C10 100n R1 +VCC U1 LM2931T-5.0 IN GND OUT 3 C11 100u 6.3V 100n R2 390 10n ISO1 R4 1 2 R5 120 R6 120 330 3 3 C14 5 6N137 100n -VEE -VEE 4 2 8 1 7 6 2 U2 VCC IN NC GND IXDI414 -VEE VCC OUT OUT GND 8 7 6 5 -VEE C13 1 10u C9 C7
PIN 1 SOURCE 100n -VEE C12 100n -VEE R3 TBD 1206 RB160M-60 R7 TBD 1206 R8 TBD 1206 C15 100n -VEE C16 100n -VEE C17 100n -VEE C18 100n -VEE C19 100n -VEE C20 10u RB160M-60 J2 BNC D2 D1 PIN 2 GATE
PULSE GEN INPUT
J1 BNC
2
VGS MONITOR
2
1
The gate driver is an IXYS IXDI414. This device has a 35 V ouput swing, output resistanceof0.6typical,andapeakcurrentcapabilityof14A.Theexternal gateresistanceusedforcharacterizationoftheSiCMOSFETwas6.8.Careful consideration needs to be given to the selection of the gate driver. The typical application error is selection of a gate driver that has adequate swing, but output
6 CMF20120D Rev. -
-VEE
resistance and current drive capability are not carefully considered. It is critical that the gate driver possess high peak current capability and low output resistance along with adequate voltage swing. AsignificantbenefitoftheSiCMOSFETistheeliminationofthetailcurrentobserved in silicon IGBTs. However, it is very important to note that the current tail does provide a certain degree of parasitic dampening during turn-off. Additional ringing and overshoot is typically observed when silicon IGBTs are replaced with SiC MOSFETs. The additional voltage overshoot can be high enough to destroy the device. Therefore, it is critical to manage the output interconnection parasitics (and snubbers) to keep the ringing and overshoot from becoming problematic.
ESD RATINGS
ESD Test
ESD-HBM ESD-MM ESD-CDM
Total Devices Sampled
All Devices Passed 1000V All Devices Passed 400V All Devices Passed 1000V
Resulting Classification
2 (>2000V) C (>400V) IV (>1000V)
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CMF20120D Rev. -
Electrical Characteristics
Symbol
V(BR)DSS VGS(th) IDSS IGSS RDS(on) gfs Ciss Coss Crss td(on)i tr td(off)i tfi EON EOff RG
Parameter
Drain-Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate-Source Leakage Current Drain-Source On-State Resistance Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Switching Loss Turn-Off Switching Loss Internal Gate Resistance (25C) (125C) (25C) (125C)
Min.
1200
Typ.
2.5 1.8 1 10 80 95 7.3 6.8 1915 120 13 17.2 13.6 62 35.6 530 422 320 329 5
Max. Unit
V 4 100 250 250 110 130
Test Conditions
VGS = 0V, ID=100A VDS = VGS, ID = 1mA, TJ = 25C VDS = VGS, ID = 1mA, TJ = 125C VDS = 1200V, VGS = 0V, TJ = 25C VDS = 1200V, VGS = 0V, TJ = 125C VGS = 20V, VDS = 0V VGS = 20V, ID = 20A, TJ = 25C VGS = 20V, ID = 20A, TJ = 125C VDS= 20V, IDS= 20A, TJ = 25C VDS= 20V, IDS= 20A, TJ = 125C VGS = 0V
Note
V
A nA m S
1
fig.3
pF
VDS = 800V f = 1MHz VAC = 25mV VDD = 800V
fig.5
ns
VGS = -2/20V ID = 20A RG=6.8 fig.12
J J
L = 856H Per JEDEC24 Page 27
VGS = 0V, f = 1MHz, VAC = 25mV
NOTES: 1. The recommended on-state VGS is +20V and the recommended off-state VGS is between -2V and -5V
Reverse Diode Characteristics
Symbol
Vsd trr Qrr Irrm
Parameter
Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Peak Reverse Recovery Current
Typ.
3.5 3.1 220 142 2.3
Max.
Unit
V ns nC A VGS
Test Conditions
= -5V, IF=10A, TJ = 25C VGS = -2V, IF=10A, TJ = 25C VGS = -5V, IF=20A, TJ = 25C VR = 800V, diF/dt=100A/s
Note
fig.13,14
Thermal Characteristics
Symbol
RJC RCS RJA
Parameter
Thermal Resistance from Junction to Case Case to Sink, w/ Thermal Compound Thermal Resistance From Junction to Ambient
Typ.
0.58 0.25
Max.
0.7
Unit
Test Conditions
Note
C/W 40
fig.6
Gate Charge Characteristics
Symbol
Qgs Qgd Qg
Parameter
Gate to Source Charge Gate to Drain Charge Gate Charge Total
Typ.
23.8 43.1 90.8
Max.
Unit
nC
Test Conditions
VDD = 800V ID =20A VGS = -2/20V Per JEDEC24-2
Note
fig.9
8
CMF20120D Rev. -
Typical Performance
120
120
100
VGS=
20V
V
100
VGS=
20V V
80
18 VGS=
80
18 VGS=
6V VGS=1
ID (A)
ID (A)
60
6V VGS=1
60
V VGS=14
40
VGS=14V
VGS=12V
40
VGS=12V
20
VGS=10V
0 0 2 4 6 8 10 12 14 16 18 20
20
VGS=10V
0 0 2 4 6 8 10 12 14 16 18 20
VDS (V)
VDS (V)
Fig 1. Typical Output Characteristics TJ = 25C
60
Fig 2. Typical Output Characteristics TJ = 125C
2 1.8
50
1.6
40
Normalized RDS(on)
1.4
T = 125C
ID (A)
30
1.2 1 0.8 0.6 0.4 0.2
VGS=20V
20
T = 25C
10
0 0 2 4 6 8 10 12 14 16 18 20
0 0 25 50 75 100 125 150
VGS (V)
T (oC)
Figure 3. Typical Transfer Characteristics
1.0E-08 VGS = 0 V f = 1 MHz
Fig 4. Normalized On-Resistance vs. Temperature
1.0E-08 VGS = 0 V f = 1 MHz
Ciss
1.0E-09
Ciss
1.0E-09
Capacitance (F)
Coss
Capacitance (F)
Coss
1.0E-10
1.0E-10
Crss
Crss
1.0E-11 0 20 40 60 80 100 120 140 160 180 200
1.0E-11
VDS (V)
0
100
200
300
400
500
600
700
800
VDS (V)
Fig 5A and 5B. Typical Capacitance vs. Drain - Source Voltage
9
CMF20120D Rev. -
Typical Performance
1.E+00
1.E-01
Zth (oC/W)
1.E-02
1.E-03
1.E-04 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01
Time (s)
Fig 6. Transient Thermal Impedence, Junction - Case
Turn-on Loss
600
Turn-off Loss
600 500
Switching Loss (J)
500
Switching Loss (J)
400
VGS= -2/20V RG= 11.8Total VDD= 800V ID= 20A
400
300
300
VGS= -2/20V RG= 11.8Total VDD= 800V ID= 20A
200
200
100
100
0 0 25 50 75 Temp ( C) 100 125 150
0 0 25 50 75 Temp ( C) 100 125 150
Fig 7. Inductive Switching Energy(Turn-on) vs. T
Fig 8. Inductive Switching Energy(Turn-off) vs. T
25 2500
25 20 15
VGS (V)
VDS
20 2000
IDS
VDD=800V
10 5
10
1000
EAS = 2.20 J
5 500
0 -5 0 20 40 60 80 100
Gate Charge (nC)
0 0 0.001 0.002
0
Time (s)
0.003
0.004
0.005
0.006
Fig 9. Typical Gate Charge Characteristics @ 25C
Fig 10. Typical Avalanche Waveform
10
CMF20120D Rev. -
VDS (V)
IDS (A)
ID=20A
15
1500
Clamped Inductive Switch Testing Fixture
tw
VGS(on) 90%
pulse duration
90% 50% 10%
Input (Vi)
50% 10%
856H + 800V 42.3f
C2D10120D 10A, 1200V SiC Schottky
VGS(off)
Input Pulse Rise Time
Input Pulse Fall Time
td(on)i
tfi
td(off)i
tri
CMF20120D D.U.T.
iD(on)
10%
10%
Output (iD)
90% iD(off) ton(i) toff(i) 90%
Fig 11. Switching Waveform Test Circuit
Fig 12. Switching Test Waveform Times
trr Ic
trr Qrr= id dt tx
tx 10% Vcc Vpk Irr 10% Irr Vcc
856H + 800V 42.3f
CMF20120D D.U.T.
Diode Recovery Waveforms
CMF20120D
t2 Erec= id dt t1
Diode Reverse Recovery Energy t1 t2
Fig 13. Body Diode Recovery Waveform
Fig 14. Body Diode Recovery Test
11
CMF20120D Rev. -
EA = 1/2L x ID2
Fig 15. Avalanche Test Circuit Fig 16. Theoretical Avalanche Waveform
Package Dimensions
Package TO-247-3
POS A A1 A2 b b1 b2 b3 b4 c D D1 D2 E E1 E2 E3 E4 e Min .190 .090 .075 .042 .075 .075 .113 .113 .022 .819 .640 .037 .620 .516 .145 .039 .487 Inches Max .205 .100 .085 .052 .095 .085 .133 .123 .027 .831 .695 .049 .635 .557 .201 .075 .529 Millimeters Min 4.83 2.29 1.91 1.07 1.91 1.91 2.87 2.87 0.55 20.80 16.25 0.95 15.75 13.10 3.68 1.00 12.38 Max 5.21 2.54 2.16 1.33 2.41 2.16 3.38 3.13 0.68 21.10 17.65 1.25 16.13 14.15 5.10 1.90 13.43
.214 BSC 3 .780 .161 .138 .216 .238 .800 .173 .144 .236 .248
5.44 BSC 3 19.81 4.10 3.51 5.49 6.04 20.32 4.40 3.65 6.00 6.30
D D D
N L L1 OP
G G G
Q S
S S S
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CMF20120D Rev. -
Recommended Solder Pad Layout
TO-247-3
Part Number
CMF20120D
Package
TO-247-3
"The levels of environmentally sensitive, persistent biologically toxic (PBT), persistent organic pollutants (POP), or otherwise restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS), as amended through April 21, 2006.
This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited toequipmentusedintheoperationofnuclearfacilities,life-supportmachines,cardiacdefibrillatorsorsimilaremergencymedical equipment,aircraftnavigationorcommunicationorcontrolsystems,airtrafficcontrolsystems,orweaponssystems. Copyright (c) 2010-2011 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo, Z-REC and Z-FET are registered trademarks of Cree, Inc.
Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5300 Fax: +1.919.313.5451 www.cree.com/power
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CMF20120D Rev. -

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